1. Technical Field of the Invention
This disclosure relates to a method for forming interconnection of semiconductor device, and more specifically, to a method for forming a pad for inputting/outputting external signal and a fuse for selective switching of circuit.
2. Description of the Related Art
A semiconductor device includes a plurality of unit devices formed on a substrate and interconnections electrically connected to the unit devices according to the designed layout. In addition, the semiconductor device includes pads for inputting/outputting power and electrical signals in order to perform cartelistic functions, and fuses in redundancy circuits for changing modules or unit devices that fail an electrical test.
Conventional methods for forming fuses in aluminum interconnection process have been disclosed by a variety of technical literature and patent specifications. Moreover, various fuse forming processes are applied to fabricate the semiconductor. Recently, a copper dual damascene process was employed in order to achieve high-rate operation, high-quality signal output, and reduction of production cost in the fabrication of semiconductor devices. A metal such as aluminum is sometimes used instead of copper because copper is relatively difficult to form while aluminum is relatively easy.
Various methods for forming fuses of semiconductor devices are disclosed in U.S. Pat. No. 5,444,012 “METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FUSE ELEMENT”, U.S. Pat. No. 6,440,833 “METHOD OF PROTECTING A COPPER PAD STRUCTURE DURING A FUSE OPENING PROCEDURE”, etc.
FIGS. 1 through 3 are cross-sectional diagrams illustrating a conventional method for forming a fuse.
Referring to FIG. 1, an interconnection 12a and fuse electrodes 12b are formed on a semiconductor substrate 10. An interlayer dielectric layer 14 is formed on the semiconductor substrate 10 over the interconnection 12a and the fuse electrodes 12b. A fuse pattern 24 is formed on the interlayer dielectric layer 14. The fuse pattern 24 electrically connects a pad pattern 22 and the fuse electrodes 12b, which are connected to the interconnection 12a through the interlayer dielectric layer 14. The interconnection 12a, the fuse electrode 12b, the pad pattern 22, and the fuse pattern 24 may be formed by a conventional dual damascene process.
Referring to FIG. 2, a passivation layer 28 is formed on the pad pattern 22 and the fuse pattern 24. The passivation layer 28 may be formed of a plurality of insulating layers according to a desired device condition and process condition.
The passivation layer 28 is patterned to form a pad opening 30 over a portion of the pad pattern 22. Simultaneously, the passivation layer 28 on the fuse pattern 24 is partially etched to form a fuse opening 34. Part of the passivation layer 28 is left on the fuse pattern 24 in the fuse opening 34.
Referring to FIG. 3, a metal layer (not shown) is formed on the passivation layer 28 over the pad opening 30 and the fuse opening 34. The metal layer is patterned to form a metal pad 32p electrically connected to the interconnection 12a. As illustrated in FIG. 3, spacers 32r from the metal layer are also formed on sidewalls of the fuse opening 34. The spacers 32r may cause problems during fusing procedures that use laser or high-voltage pulses. For example, if the spacers 32r are connected along edges of the fuse opening 34, the spacer may electrically connect the fuse electrodes 12b even when the fuse pattern 24 is blown in a fusing procedure.
In addition, if the passivation layer 28 on the fuse pattern 24 suffers from over-etching while the metal pad 32p is formed, laser scattering occurs at the surface 36 of the insulating layer and sufficient energy for blowing a fuse may not be provided to the fuse pattern 24. In addition, because the pad opening 30 and the fuse opening 34 are simultaneously formed, the passivation layer 28 in the pad opening needs to be over-etched because the insulating layer should not remain on the pad pattern 22. As a result, the thickness of the remaining passivation layer 28 in the fuse opening 34 is difficult to control.
Embodiments of the invention address these and other disadvantages of the prior art.